1. Field of the Invention
The present invention generally relates to alarm detection apparatuses, and more particularly to an alarm detection apparatus which detects and/or cancels an alarm depending on an error rate of a data communication line.
In systems such as a Synchronous Optical Network (SONET) or a Synchronous Digital Hierarchy (SDH), a quality of a digital line is monitored by use of a B2 byte (BIP: Bit Interleaved Parity-8) or a B2 byte (BIP-8.times.N(in the case of the SONET)/BIP-N.times.24 (in the case of the SDH) of a frame format. The present invention is suited for application to such systems.
2. Description of the Related Art
FIG. 1 is a diagram showing a frame format of a SONET Synchronous Transport Signal-N (STS-N) for a case where N=192. At a transmitting end, a BIP operation result indicated by a hatched portion of an nth frame before scrambling is inserted into the B2 byte of a (n+1)th frame before the scrambling. On the other hand, at a receiving end, a BIP operation result with respect to the nth frame after descrambling thereof and a B2 byte of the (n+1)th frame after descrambling are compared, so as to detect a BIP error. According to STS-192, 1 B2 byte is multiplexed 192 times, and BIP-8.times.192 (8.times.192=1536 bits) BIP operations are carried out in total. Although not shown in FIG. 1, BIP operation and monitoring are similarly carried out with respect to the B1 byte, although an operation range differs from that for the B2 byte.
For the sake of convenience, the error rate will be described with respect to the BIP-8 of the STS-1 in order to simplify the description. The error rate for a case where only 1 bit within 1 frame is in error and no error exists in the other bits can be described by 1/(801.times.8)=1/6408.noteq.1.5.times.10.sup.-4. Accordingly, it is possible to monitor whether or not the error rate is 1.times.10.sup.-9 or greater, for example, by monitoring whether or not a BIP-8 error of 1 bit exists in 1.5.times.10.sup.5 frames or, a BIP-8 error of 10 or more bits exist in 1.5.times.10.sup.6 frames. Timewise, 1 frame period of the STS-N (STM-N) is 125 .mu.sec, and thus, it requires at least approximately 19 sec in order to monitor the above error rate of 1.times.10.sup.-9. Actually, there are cases where a check is made to determine whether or not such a single bit error occurs 100 or more times so as to improve the monitoring accuracy. In such cases, the monitoring unit becomes 100 times the above period, that is, approximately 32 minutes.
FIG. 2 is a system block diagram showing a conventional alarm detector. FIG. 2 shows a typical construction which is used in common for alarm detectors 10.sub.1 through 10.sub.10 which will be described later. In FIG. 2, an error counter (ERCT) 11 counts an error bit B2E of the BIP (B2 byte), and a protection counter (PRCT) 12 counts a number of protection times of the alarm detection and/or cancellation. A frame counter (FRCT) 13 counts a frame pulse B2FP which has a period of 125 .mu.sec and is generated in synchronism with the B2 byte of the STS-N frame. A timing decoder (TDC1) 15-1 decodes a counter output Q of the frame counter 13, and generates an alarm detection timing signal (for example, 1T) which is used for alarm detection. A hysteresis counter (HYCT) 14 counts a pulse signal which is generated with a period of the alarm detection timing signal 1T. A timing decoder (TDC2) 15-2 decides a counter output Q of the hysteresis counter 14, and generates an alarm cancel detection timing signal (for example, 10T which is 10 times the period) which is used for alarm cancel detection. Comparators (CM1, CM2) 17-1 and 17-2, AND gate circuits (A1 through A5) 18-1 through 18-2, a selector (SL1) 16, edge detection circuits (EG1, EG2 and EG4 through EG6) 19-1, 19-2 and 19-4 through 19-6 for detecting rising and/or falling edges of input signals and generating edge pulse signals EP1, EP2 and the like, a flip-flop (FF1) 1 for holding an alarm detection and/or cancel state, and OR gate circuits (ORI, OR2) 2-1 and 2-2 are connected as shown in FIG. 2.
Although not shown in FIG. 2, a system clock signal CK19 is input to a clock input terminal CK or the like of each of the counters 11 through 14 and the like. In addition, a system reset signal CL is input to a reset terminal R of each of the counters 11 through 14 and the flip-flop 1.
Next, a description will be given of the operation of the alarm detector 101. The alarm detector 10.sub.1 is in an alarm detection mode when the flip-flop 1 is reset. In this case, the AND gate circuits 18-1 and 18-3 are closed, and the selector 16 selectively outputs the alarm detection timing signal 1T. As a result, the error counter 11 counts the error bit signal B2E of the B2 byte generated during an interval of the timing (gate) signal 1T. In this state, the comparator 17-1 compares the counter output Q of the error counter 11 and a predetermined threshold value which is 980, for example. When the timing signal 1T thereafter falls, the edge pulse signal EP1 is generated in synchronism with this fall of the timing signal 1T, and if the counter output Q of the error counter 11 is greater than or equal to 980 at this timing, the AND gate circuit 18-1 is opened and the protection counter 12 is incremented by +1. If the counter output Q of the error counter 11 is consecutively greater than or equal to 980 with respect to each detection period 1T, the protection counter 12 is incremented by +1 each time. However, if the counter output Q of the error counter 12 becomes less than 980 at least once during the above time, the protection counter 12 is reset and the count is restarted from the beginning. In this state, the comparator 17-2 compares the counter output Q of the protection counter 12 and a predetermined threshold value which is 58, for example. Hence, if the counter output Q of the protection counter 12 is greater than or equal to 58 at the timing of each edge pulse signal EP2 following the edge pulse signal EP1, the AND gate circuit 18-3 is opened and the flip-flop 1 is set to thereby output an alarm detection signal ALD1=1. In addition, when the flip-flop 1 is set, the protection counter 12 is reset, and the alarm detector 10.sub.1 then assumes an alarm cancel detection mode.
In the alarm cancel detection mode, the AND gate circuits 18-2, 18-4 and 18-5 are closed, and the selector 16 selectively outputs the alarm cancel detection timing signal 10T. Hence, the error counter 11 counts the error bit signal B2E of the B2 byte generated during an interval of the timing (gate) signal 10T. In this state, the comparator 17-1 compares the counter output Q of the error counter 11 and the and a predetermined threshold value which is 980, for example. When the timing signal 10T thereafter falls, the edge pulse signal EP1 is generated in synchronism with this fall of the timing signal 10T, and if the counter output Q of the error counter 11 is less than 980 at this timing, the AND gate circuit 18-2 is opened and the protection counter 12 is incremented by +1. If the counter output Q of the error counter 11 is consecutively less than 980 with respect to each detection period 10T, the protection counter 12 is incremented by +1 each time. However, if the counter output Q of the error counter 12 becomes greater than or equal to 980 at least once during the above time, the protection counter 12 is reset and the count is restarted from the beginning. In this state, the comparator 17-2 compares the counter output Q of the protection counter 12 and a predetermined threshold value which is 58, for example. Hence, if the counter output Q of the protection counter 12 is greater than or equal to 58 at the timing of each edge pulse signal EP2 following the edge pulse signal EP1, the AND gate circuit 18-4 is opened and the flip-flop 1 is reset to thereby output an alarm detection signal ALD1=0. In addition, when the flip-flop 1 is reset, the protection counter 12 is reset, and the alarm detector 10.sub.1 then assumes the alarm detection mode.
FIG. 3 is a diagram showing various kinds of setting information for making the alarm detection and/or cancellation. In FIG. 3, in a case where the detected error rate is 10.sup.-3, it is a condition for that alarm detection that the number of errors within 1 frame interval (1T) is greater than or equal to 980 and that this state continues for 58 times or more. The detection time for this case is 7.25 msec. On the other hand, 10 times the period (10T) of the alarm detection is employed for the alarm cancel detection in this case, and a so-called hysteresis control is carried out such that the monitoring conditions are different between the alarm detection and the alarm cancel detection. That is, the condition of the alarm cancel detection is that the number of errors within 10 frames (10T) becomes less than 980 consecutively for 58 or more times. Similar conditions are determined with respect to other error rates of 10.sup.-4 through 10.sup.-10, and examples of the monitoring conditions with respect to each of the error rates are shown in FIG. 3.
FIG. 4 is a system block diagram showing a conventional alarm detection apparatus. FIG. 4 shows the construction for realizing the monitoring conditions shown in FIG. 3. In FIG. 4, a major detector unit 21 detects major alarms MAJALM in the system, and includes alarm detectors 10.sub.1 through 10.sub.3 which respectively detect a relatively large number of error rates 10.sup.-3 through 10.sup.-5. A selector (SL1) 23 selectively outputs one of alarm signals MAAL1 through MAAL3 depending on a major detection selection signal MAJRT [1-3] which is input to the system. Hence, the system can monitor the existence of a desired one of the major error rates which is generated. A minor detector unit 22 detects minor alarms MINALM in the system, and includes alarm detectors 10.sub.4 through 10.sub.10 which respectively detect a relatively small number of error rates 10.sup.-4 through 10.sup.-10. A selector (SL2) 24 selectively outputs one of alarm signals MIAL1 through MIAL8 depending on a minor detection selection signal MINRT [1-7] which is input to the system. Hence, the system can monitor the existence of a desired one of the minor error rates which is generated. An OR gate circuit (OR1) 25 receives a system reset signal RST and a minor reset signal MINRST which will be described later.
A monitoring function of the major detector unit 21 is reset by the system reset signal RST such as a power ON reset signal. On the other hand, a monitoring function of the minor detector unit 22 is reset by the system reset signal RST or the minor reset signal MINRST. The minor reset signal MINRST is generated when a signal disconnection LOS of the line, a synchronization error LOF of the STS-N frame or the like is detected by the system. When a large number of faults is generated, it is sufficient to activate the functions of the major detector unit 21, and the functions of the minor detector unit 22 are deactivated.
In the major detector unit 21, the alarm detection signal MAAL1 from an output terminal ALD of the alarm detector 101 is input to an input terminal ALI of the alarm detector 10.sub.2, and the alarm detection signal MAAL2 from an output terminal ALD of the alarm detector 10.sub.2 is input to an input terminal ALI of the alarm detector 10.sub.3. The alarm detection signals MAAL1 and MAAL2 are input to the edge detection circuit (EG5) 19-5 shown in FIG. 2, and act so as to forcibly set the flip-flop (FF1) 1 in synchronism with the rising edge thereof. Hence, if an alarm signal of the error rate of 10.sup.-4 is detected in FIG. 4, the alarm signal of the error rate of 10.sup.-5 is forcibly set at the same time. In addition, if an alarm signal of the error rate of 10.sup.-3 is detected, the alarm signals of the error rates of 10.sup.-4 and 10.sup.-5 are forcibly set at the same time. Accordingly, even if the detecting conditions (periods) differ among the alarm detectors 10.sub.1 through 10.sub.3, when an alarm of a relatively high error rate is detected, all alarms of error rates lower than this relatively high error rate are also detected at the same time, so that detections reasonably adapted to the actual error generation state is realized. Similar detections are also made in the minor detector unit 22.
On the other hand, in the major detector unit 21, it is known to input the alarm detection signal MAAL1 from the most significant alarm detector 10.sub.1 to input terminals MAAL1 of each of the less significant alarm detectors 10.sub.2 and 10.sub.3 as indicated by a dotted line in FIG. 4. The alarm detection signal MAAL1 from the most significant alarm detector 10.sub.1 is input to the edge detection circuit (EG6) 19-6 which resets or initializes the hysteresis counter 14 and the protection counter 12 in response to the falling edge of the alarm detection signal MAAL1, that is, in response to the alarm cancel detection, as indicated by a dotted line in FIG. 2. Hence, when the alarm detection signal MAAL1 from the most significant alarm detector 10.sub.1 shown in FIG. 4 is cancelled, the detection phases for the alarm cancellation in each of the less significant alarm detectors 10.sub.2 and 10.sub.3 are simultaneously synchronized to the cancellation timing of the alarm detection signal MAAL1 from the most significant alarm detector 10.sub.1, and the detecting operations for the alarm cancellation are simultaneously started. Although not shown in FIG. 4, it is of course possible to construct the minor detector unit 22 similarly to the major detector unit 21 described above.
But in the conventional system described above, in a case where the error rates such as the error rates 10.sup.-4 and 10.sup.-5 to be detected by the major detector unit 21 and the minor detector unit 22 overlap, no problems will occur if the detection and/or cancellation timings of the major detector unit 21 and the minor detector unit 22 match, however, the detection and/or cancellation timings may not necessarily match. For example, the detection and/or cancellation timings will not match if the reset conditions of the major detector unit 21 and the minor detector unit 22 are different. When the detection and/or cancellation timings of the major detector unit 21 and the minor detector unit 22 are different, there is a problem in that the same kind of alarm signal will be detected and/or be cancelled at different timings within the system.
In addition, according to the conventional system described above which synchronizes the alarm cancel detection timings of each of the less significant alarm detectors 10.sub.2 and 10.sub.3 to the cancellation timing of the alarm detection signal MAAL1 from the most significant alarm detector 10.sub.1, the following problems occur.
FIGS. 5 and 6 are timing charts for explaining the operation of the conventional alarm detection apparatus. In FIGS. 5 and 6, it is assumed for the sake of convenience that the detection period is 1T, 3T and 5T in the most significant order, and that no hysteresis control is carried out for the alarm cancel detection.
FIG. 5 shows a case where an error B2E generated at a high density disappears quickly. The most significant alarm signal ALD1 is quickly set by the generation of the high density burst error, and the less significant alarm signals ALD2 and ALD3 are simultaneously set forcibly in response to the setting of the most significant alarm signal ALD1. Next, when the most significant alarm signal ALD1 is quickly reset (cancelled) due to a rapid decrease of the error generation density, the phases of the alarm cancel detection timing signals 3T and 5T for the less significant alarms are synchronized to the cancellation timing of the alarm signal ALD1. Hence, in this particular case, the alarm signal ALD2 is cancelled at a timing 3T after the cancellation of the most significant alarm signal ALD1, and the alarm signal ALD3 is cancelled at a timing 5T after the cancellation of the most significant alarm signal ALD1. Consequently, it is possible to quickly carry out the alarm detection and/or cancellation operation which is adapted to the actual generation and/or disappearance of the error B2E.
On the other hand, FIG. 6 shows a case where the error B2E generated at a high density gradually reduces its generation rate and disappears. The most significant alarm signal ALD1 is quickly set by the generation of the high density burst error, and is reset quickly as the density thereafter decreases. With respect to the alarm signal ALD2, the alarm cancel detection is started in synchronism with the cancellation timing of the most significant alarm signal ALD1. However, the error density is greater than or equal to a first predetermined value in the first 3T interval and the alarm signal ALD2 is not reset in this first 3T interval, and is finally reset in the second 3T interval. With respect to the alarm signal ALD3, the alarm cancel detection is started in synchronism with the cancellation timing of the most significant alarm signal ALD1. However, the error density is greater than or equal to a second predetermined value which is lower than the first predetermined value in the first and second 5T intervals and the alarm signal ALD3 is not reset in these first and second 5T intervals, and is finally reset in the third 5T interval. Accordingly, there is a problem in that the less significant alarm signal ALD3 is not reset for a considerably long time. This problem is caused by the overlap of the alarm cancel detection timings between the less significant alarm detectors 10.sub.2 and 10.sub.3, and because the error bit B2E in the intervals are taken into account for the evaluation by both of the alarm detectors 10.sub.2 and 10.sub.3. In this particular case, the periods of the alarm detection cancellation are 1T, 3T and 5T, but the periods of the actual alarm detection cancellation are generally much larger and are 10T, 100T and 1000T, for example. As a result, the differences among the periods of the actual alarm detection cancellation is extremely large, thereby making the delay of the alarm cancel detection no longer negligible.
Furthermore, as shown in FIG. 2, when each alarm detector 10 is constructed to include the frame counter 13 and the hysteresis counter 14, there is a problem in that the circuit scale of the frame counter 13 and the hysteresis counter 14 becomes larger for the alarm detectors provided for the lower error rates as compared to the alarm detectors provided for the higher error rates. In other words, the most significant alarm detector 10.sub.1 shown in FIG. 2 simply generates the alarm detection timing signal 10T and the alarm cancel detection timing signal 10T based on the frame pulse signal B2FP, but the least significant alarm detector 10.sub.10 shown in FIG. 4 must generate the alarm detection and alarm cancel detection timing signals 4000000T based on the frame pulse signal B2FP. For this reason, a large scale counter circuit is required in the alarm detection apparatus as a whole. Further, since the scale of the counter differs for each alarm detector 10, there is another problem in that a common circuit construction cannot be used for each of the alarm detectors 10.